An important property of high performance semiconductor devices is the ability to conduct electricity. Current is inversely related to resistance. Traditionally, increasing the cross-section of the semiconducting material, shortening the length for the electron path, increasing the voltage, or decreasing the resistivity of the semiconducting material can all decrease resistance and increase electron flow through electrical devices.
In order to be able to make integrated circuits (ICs), such as memory, logic, and other devices, of higher integration density than currently feasible, one has to find ways to further downscale the dimensions of field effect transistors (FETs), such as metal-oxide-semiconductor field effect transistors (MOSFETs) and complementary metal oxide semiconductors (CMOS). Scaling achieves compactness and improves operating performance in devices by shrinking the overall dimensions and operating voltages of the device while maintaining the device's electrical properties. Additionally, all dimensions of the device must be scaled simultaneously in order to optimize electrical performance of a device.
One of the primary challenges to FET scaling is lowering the device's contact resistance, e.g., external resistance (also known as source/drain resistance). External resistance is the sum of all of the resistance values in a MOSFET device except for channel resistance. The external resistance is attributed to doping and diffusion of the wafer as well as the silicidation process. When scaling MOSFET devices, and if the device gate-length and the gate dielectric thickness are reduced and the contact resistance is held constant, then the performance benefits achieved through scaling will be limited.
The problem of contact resistance is not limited to FETs devices. A similar problem exists, for example, in interconnect structures in which at least one conductive filled region of an upper interconnect level mates with another conductive filled region of a lower interconnect level. As the size of these structures decrease, the area of contact is scaled in a similar manner inducing increasing contact resistance.
In view of the above, there is a continued need for providing semiconductor structures in which the contact resistance of the structure has been improved, i.e., reduced.